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utc CD4541 cmos ic utc unisonic technologies co., ltd. 1 www.unisonic.com.tw qw-r502-037,a programmable timer description the utc CD4541 programmable timer comprise a 16-stage binary counter, an integrat ed oscillator for use with an external capacitor and two re sistors, output control logic, and a special power-on reset circuit. the counter divides the oscillator frequency by any of 4 digitally controlled division ratios. features *operates at 2 n frequency divider or as single transition timer *increments on positive edge clock transitions *wide supply voltage range: 3.0v ~ 15v *built-in low power rc oscillator *oscillator frequency range ~ dc to 100 khz *external clock applied to pin 3 can be used instead of oscillator * available division ratios 2 8 , 2 10 , 2 13 , or 2 16 *high noise immunity: 0.45 v dd (typ.) *master reset totally independent of automatic reset operation *automatic reset initializes all counters when power turns on *q/q select provides output logic level flexibility *high output drive min. one ttl load *maximum input leakage 1 ? a at 15v over full temperature range dip-14 sop-14 *pb-free plating product number: CD4541l pin configuration mr n.c. ar rs a v dd b rtc mode q/q select q vss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 ctc n.c.
utc CD4541 cmos ic utc unisonic technologies co., ltd. 2 www.unisonic.com.tw qw-r502-037,a truth table state pin 0 1 5 auto reset operating auto reset disabled 6 timer operational master reset on 9 output initially low after reset output initially high after reset 10 single cycle mode recycle mode division ratio table a b number of counter stages n count 2 n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 block diagram a 12 b 13 rtc 1 ctc 2 rs 3 auto reset 5 power-on reset master reset 10 mode 9 q/q select 8 q 1 of 3 mux 2 10 2 13 2 16 c b-stage counter reset c 8-stage counter 2 8 reset osc reset v dd =pin 14 vss=pin 7 6
utc CD4541 cmos ic utc unisonic technologies co., ltd. 3 www.unisonic.com.tw qw-r502-037,a absolute maximum ratings (note 1, 2) parameter symbol ratings unit supply voltage v dd -0.5 ~ +18 v input voltage v in -0.5 ~ v dd +0.5 v dip-14 700 power dissipation sop-14 p d 500 mw lead temperature (soldering, 10 seconds) t l 260
storage temperature range t stg -65 ~ +150
recommended operating conditions (note 2) parameter symbol ratings unit supply voltage v dd 3 ~ 15 v input voltage v in 0 ~ v dd v operating temperature range t opr -40 ~ +85
note 1: ?absolute maximum ratings? are those values beyond which the safety of t he device cannot be guaranteed. except for ?operating temperatur e range? they are not meant to imply that the devices should be operated at these limits. the table of ?electrical characteristi cs? provides conditions for actual device operation. note 2: v ss =0v unless otherwise specified. dc electrical characteristics (note 2, ta=25
, unless otherwise noted.) parameter symbol test conditions min typ max unit quiescent device current i dd v dd =5v, v in =v dd or vss v dd =10v, v in =v dd or vss v dd =15v, v in =v dd or vss 0.005 0.010 0.015 20 40 80 ? a low level output voltage v ol v dd =5v v dd =10v, i i o i<1 ? a v dd =15v 0 0 0 0.05 0.05 0.05 v high level output voltage v oh v dd =5v v dd =10v, i i o i<1 ? a v dd =15v 4.95 9.95 14.95 5 10 15 v low level input voltage v il v dd =5v, vo=0.5v or 4.5v v dd =10v, vo=1.0v or 9.0v v dd =15v, vo=1.5v or 13.5v 2 4 6 1.5 3.0 4.0 v high level input voltage v ih v dd =5v, vo=0.5v or 4.5v vdd=10v, vo=1.0v or 9.0v v dd =15v, vo=1.5v or 13.5v 3.5 7.0 11.0 3 6 9 v low level output current (note 3) i ol v dd =5v, vo=0.4v v dd =10v, vo=0.5v v dd =15v, vo=1.5v 1.96 2.66 10.4 3.6 9.0 34.0 ma high level output current (note 3) i oh v dd =5v, vo=2.5v v dd =10v, vo=9.5v v dd =15v, vo=13.5v 4.27 2.25 8.8 130 8.0 30.0 ma input current i in v dd =15v, v in =0v v dd =15v, v in =15v -10 -5 10 -5 -0.3 0.3 ? a note 3: i oh and i ol are tested one output at a time.
utc CD4541 cmos ic utc unisonic technologies co., ltd. 4 www.unisonic.com.tw qw-r502-037,a ac electrical characteristics (note 4, ta=25
, cl=50pf (refer to test circuits)) parameter symbol test conditions min typ max unit output rise time t tlh v dd =5v v dd =10v v dd =15v 50 30 25 200 100 80 ns output fall time t thl v dd =5v v dd =10v v dd =15v 50 30 25 200 100 80 ns turn-off, turn-on propagation delay, clock to q (2 8 output) t plh , t phl v dd =5v v dd =10v v dd =15v 1.8 0.6 0.4 4.0 1.5 1.0 ? s turn-on, turn-off propagation delay, clock to q (2 16 output) t phl , t plh v dd =5v v dd =10v v dd =15v 3.2 1.5 1.0 8.0 3.0 2.0 ? s clock pulse width t wh(cl) v dd =5v v dd =10v v dd =15v 400 200 150 200 100 70 ns clock pulse frequency f cl v dd =5v v dd =10v v dd =15v 2.5 6.0 8.5 1.0 3.0 4.0 mhz mr pulse width t wh(r) v dd =5v v dd =10v v dd =15v 400 200 150 170 75 50 ns average input capacitance c i any input 5.0 7.5 pf power dissipation capacitance (note 5) c pd 100 pf note 4: ac parameters are guaranteed by dc correlated testing. note 5: c pd determines the no load ac power c onsumption of any cmos device.
utc CD4541 cmos ic utc unisonic technologies co., ltd. 5 www.unisonic.com.tw qw-r502-037,a operating characteristics with auto reset pin set to a ?0? the counter circuit is initialized by turning on power. or with power already on, the counter circuit is reset when the master reset pin is set to a ?1?. both types of reset will result in synchronously resetting all counter stages independent of count er state. the rc oscillator frequency is determined by the external rc network, i.e.: if (1 khz f 100khz) f= 2.3 rtcctc 1 and rs ~ 2 rtc where rs 10 k ? the time select inputs (a and b) provide a two-bi t address to output any one of four counter stages (2 8 , 2 10 , 2 13 , and 2 16 ). the 2 n counts as shown in the division ratio table repres ent the q output of the nt h stage of the counter. when a is ?1?, 2 16 is selected for both states of b. however, when b is ?0?, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8 ). the q/q select output control pin provid es for a choice of output level. w hen the counter is in a reset condition and q/q select pin is set to a ?0? the q output is a ?0?. correspondingly, when q/q select pin is set to a ?1? the q output is a ?1?. when the mode control pin is set to a ?1?, the selected count is continually transmi tted to the output. but, with mode pin ?0? and after a reset condition the rs flip-flop resets (see logic diagram), counting commences and after 2 n-1 counts the rs flip-flop sets wh ich causes the output to change state. hence, after another 2 n-1 counts the output will not change. thus, a master reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. rc oscillator frequency as a function of r tc and c resistance , r tc ( k $ dscillator frequency,f (khz) v dd = 10v f as a function of c and (r tc =5 6 k $ , rs =120k 70 dscillator frequency,f (khz) v dd =10v capacitance, c (f) f as a function of r tc and (c=100pf, rs=2 r tc 1.0k 10k 100 k 1. 0m 0. 07 0. 7 7 ) ) ) rc oscillator frequency as a function of r tc and c 0.0001 0.001 0.01 0.1 1.0k 10k 100k 1.0m
utc CD4541 cmos ic utc unisonic technologies co., ltd. 6 www.unisonic.com.tw qw-r502-037,a internal reset r tc 21 r s to clock circuit oscillator circuit using rc configuration 3 c tc test circuit and waveforms power dissipation test circuit and waveforms pulse generator rs ar q/q select mode a b mr q c l v ss (r tc and ctc outputs are left open ) v dd 50% duty cycle t wh (cl) 20 ns 20 ns 90% 50% 10% rs
utc CD4541 cmos ic utc unisonic technologies co., ltd. 7 www.unisonic.com.tw qw-r502-037,a t plh t wh (cl) 20 ns 20 ns 90% 50% 10% rs 50% t phl 50% t thl t tlh 90% 50% 10% q sw itching tim e test c ircuit and w aveform s pulse generator rs ar q/q select mode a b mr q c l v ss v dd utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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